1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data and, more particularly, to a pattern layout of transfer transistors that supply a voltage to word lines in a NAND flash memory which executes a subblock erase.
2. Description of the Related Art
EEPROMs are known as semiconductor memories that can electrically rewrite data. Of these EEPROMs, NAND EEPROMs (NAND flash memories) have received a great deal of attention because of its possibility of higher integration degree. A NAND flash memory has NAND cells each of which is formed by serially connecting a plurality of memory cells, i.e., units that store 1-bit data. NAND flash memories are used in memory cards to store, e.g., image data of digital still cameras.
Along with the recent increase in capacity of NAND flash memories, the write unit (page size) and erase unit (block capacity) are also becoming large. Generally, the block capacity of a NAND flash memory corresponds to an integer multiple (size) of the page capacity. When the block capacity increases, the efficiency in erasing or rewriting data in small capacity becomes low. To prevent this, the present applicant has proposed a method (referred to as a subblock erase) of erasing only part of the block capacity (e.g., Jpn. Pat. Appln. KOKAI Publication No. H11-177071).
In the subblock erase, since the block capacity is partially erased, data in small capacity can efficiently be erased or rewritten.
The subblock erase in a NAND flash memory will be described first.
A memory cell of a NAND flash memory has a MOSFET structure in which a floating gate and control gate (word line) are stacked, via an insulating film, on a semiconductor substrate serving as a channel region. A NAND cell is formed by serially connecting a plurality of memory cells while making adjacent memory cells share the source/drain. The source/drain means an impurity region having at least one of the functions of the source and the drain.
FIG. 1 shows the memory cell array of a NAND flash memory and some of its peripheral circuits. One NAND cell 4a of the NAND flash memory includes two select transistors S1 and S2 and memory cells MC0 to MCi. The gates of the select transistors S1 and S2 are connected to select gate lines SGS and SGD, respectively. The current paths of the memory cells MC0 to MCi are connected in series between the select transistors S1 and S2. The control gates of the memory cells MC0 to MCi are connected to word lines WL0 to WLi, respectively. One end of the current path of each of the select transistors S1 is commonly connected to a source line CELSRC. One end of the current path of each of the select transistors S2 is connected to a corresponding one of bit lines BL0 to BLj. The control gates of cell transistors acting as the memory cells MC0 to MCi and the gates of the select transistors S1 and S2 are commonly connected to the control gate lines (word lines WL0 to WLi) and select gate lines SGS and SGD, which are arranged in the row direction of a memory cell array MCA, for each row.
An erase unit means a set 4b of memory cells MC which belong to the NAND cell 4a and are connected to a predetermined number of word lines WL. A set of the memory cells MC0 to MCi connected to all the word lines WL0 to WLi, including the erase units 4b, and the select transistors S1 and S2 will be referred to as a block (NAND cell block) 4 or 4′. That is, each block 4 or 4′ includes a plurality of erase units 4b or 4b′.
The word lines WL0 to WLi in the block 4 have transfer transistors (word line transfer transistors) Tr0 to Tri, respectively. The drain of each of the transfer transistors Tr0 to Tri is connected to a corresponding one of the word lines WL0 to WLi so that a voltage is supplied to the word lines WL0 to WLi. The gates of the transfer transistors Tr0 to Tri are commonly connected to a node G. The source of each of the transfer transistors Tr0 to Tri is connected to a corresponding one of word line driving signal lines (driving lines) CG0 to CGi. The word line transfer transistors Tr0 to Tri construct a part of a row decoder.
The remaining blocks (e.g., the block 4′) also have the same structure as that of the block 4.
FIG. 2 is a schematic view for explaining voltage application conditions in the erase in the NAND cell 4a. The data erase is executed in the following way. A ground potential is applied to all control gates (word lines WL0 to WLi) in the selected block. All control gates in unselected blocks and the select gate lines SGS and SGD, bit lines BL0 to BLj, and source lines CELSRC in all blocks are set in a floating state. Then, a high erase potential (about 20V) is applied to the well regions of the cells MC0 to MCi. Accordingly, in the cells MC0 to MCi in the selected block, electrons in the floating gates are drained to the well regions so that the erase is executed for one block. At this time, even in all control gates in the unselected blocks and the select gate lines SGS and SGD, bit lines BL0 to BLj, and source lines CELSRC in all blocks, the potential increases almost upto the erase potential due to capacitive coupling (for example, in the select gate line SGS, capacitive coupling occurs between the gate capacitance of the select transistor S1 and the other capacitance of the select gate line SGS against ground potential). The ground potential is supplied to the word line driving signal lines CG0 to CGi. The transfer transistors Tr0 to Tri in the selected block are turned on because a power supply voltage Vdd is applied to the node G. The ground potential is applied from the word line driving signal lines CG0 to CGi to the control gates of the cells MC0 to MCi in the selected block. In the unselected blocks, the transfer transistors are turned off because the ground potential is applied to the node G. The control gates of the cells MC0 to MCi in the unselected blocks are set in the floating state.
FIG. 3 is a schematic view showing voltage application conditions in the subblock erase in the NAND cell 4a. In this example, the memory cells MC0, MC1, MC2, and MC3 are erased. In the subblock erase, in the selected block, the ground potential is applied to the control gates (word lines) of the cells to be erased, and the control gates of cells not to be erased are set in the floating state. All control gates in unselected blocks and the select gate lines, bit lines, and source lines in all blocks are set in the floating state. Then, a high erase potential (about 20V) is applied to the well regions of the cells. Accordingly, in the cells to be erased in the selected block, electrons in the floating gates are drained to the well regions so that the erase is executed for each selected control gate line. At this time, even in all control gates in the unselected blocks and the select gates, bit lines, and source lines in all blocks, the potential increases almost to the erase potential due to capacitive coupling (for example, in the select gate line, capacitive coupling occurs between the gate capacitance of the select transistor and the other capacitance of the select gate line against ground potential). The ground potential is supplied to the word line driving signal lines CG0 to CG3 corresponding to the cells to be erased. To the contrary, the power supply voltage Vdd is supplied to the word line driving signal lines CG4 to CGi corresponding to the cells not to be erased.
The transfer transistors Tr0 to Tri in the selected block are turned on because the power supply voltage Vdd is applied to the node G. The ground potential is applied to the control gates of the cells to be erased in the selected block. The control gates of the cells not to be erased are charged to “Vdd-Vtt” (Vt is the threshold voltage of the word line transfer transistors) and set in the floating state. In the unselected blocks, the transfer transistors are turned off because the ground potential is applied to the node G. The control gates in the unselected blocks are set in the floating state. The breakdown voltage of an element isolation insulating film which isolates the transfer transistors from each other must be determined on the basis of the maximum potential difference between adjacent transistors and, more specifically, a case wherein one of adjacent transistors has a potential of 20V, and the other has a potential of 0V.
As described above, in the unselected block in the erase operation, the floating state (20V) of a word line is sometimes present next to the ground potential of a word line driving signal line. In the subblock erase operation, in addition to the above case, the floating state (20V) of the word line of a cell not to be erased may be present next to the ground potential of a word line driving signal line or the ground potential of the word line of a cell to be erased. A leakage current flows between the junction portions of transistors through the element isolation insulating film between the junction portions in accordance with the potential difference between them. When a junction portion in the floating state (20V) is present next to a junction portion having the ground potential, the potential difference becomes large, and the leakage current also becomes large. When a large leakage current flows, the potential of the node in the floating state, i.e., the potential of the word line not to be erased drops. When the potential drop in the word line connected to the cell not to be erased is large, the potential difference between the well region and the gate of the cell increases, as described above, and the cell is readily erroneously erased. Especially, when the number of junction portions which have the ground potential and are present next to junction portions in the floating state (20V) is large, the potential drop is conspicuous. The leakage current between the junction portions becomes large as the width of the element isolation insulating film becomes narrow. For this reason, when the number of junction portions which have the ground potential and are present next to those in the floating state (20V) is large, the element isolation insulating film must be wide, and the area of the row decoder increases. On the other hand, as the micropatterning technology advances, the pitch of word lines decreases. Then, the width of the row decoder also decreases, and the element isolation insulating film must be narrower. The increase in area of the row decoder goes against the requirement for micropatterning.
FIG. 4 is a plan view showing a conventional pattern layout of word line transfer transistors. In this example, the number of word lines is 32 (WL0, . . . , WL31). Word line transfer transistors Tr0 to Tr31 are arrayed in three lines. The Y direction indicates the direction in which bit lines BL run. The X direction indicates the direction in which word lines WL run. In the pattern layout shown in FIG. 4, a word line transfer transistor connected to a word line is not present next to those connected to adjacent word lines. This pattern layout of word line transfer transistors takes the element isolation breakdown voltage into consideration and is described in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-141477.
FIG. 5 shows the relationship between the word line transfer transistor pattern layout and the potentials of nodes when the subblock erase is executed for cells connected to the word lines WL8, WL9, WL10, and WL11 in the cell 4b shown in FIG. 1. The transfer transistor Tr6 at 20V (floating state), which is connected to the word line WL6 of the cell not to be erased, opposes the transfer transistors Tr8, Tr9, and Tr11 at 0V in three directions, which are connected to the word lines of cells to be erased. The leakage currents between the junction portion of the transfer transistor Tr6 and those of the transfer transistors Tr13 and Tr14 do not greatly affect because the opposing area is small. However, the potential difference between the junction portion of the transfer transistor Tr6 and those of the word line transfer transistors Tr8, Tr9, and Tr11, which are adjacent in the X and Y directions, largely affects the leakage current. In the above-described case, leakage currents flow from the junction portion of the transfer transistor Tr6 to the transfer transistors Tr8, Tr9, and Tr11 in the three directions, as indicated by arrows. Each leakage current to flow through transfer transistors Tr8 and Tr9 is slightly larger than a leakage current the flow through transfer transistor Tr11. For this reason, the potential drop in the word line is maximized. The device breakdown voltage must be designed in consideration of the maximum leakage current. To do this, the width of the element isolation insulating film or the gate length of the transfer transistor must be increased. This leads to an increase in area of the row decoder.
According to an aspect of the present invention, there is provided a semiconductor device comprising a memory cell array in which electrically rewritable nonvolatile memory cells are arranged in row and columns, first word lines arranged in the memory cell array and connected to the memory cells of the respective rows, the first word lines being formed of a first interconnection extended from gate electrodes of the memory cells, second word lines corresponding to the respective first word lines, and formed of a second interconnection which is formed of a layer different from a layer of the first interconnection, and an interconnection switching region provided between the first word lines and the second word lines, the interconnection switching region connecting selected portions of the first interconnection and the second interconnection, the interconnection switching region having a multilayered interconnection structure in which the first word lines cross the second word lines to change at least part of layout positions.
According to another aspect of the present invention, there is provided a semiconductor device comprising a memory cell array in which memory cells are arranged, first word lines connected to the memory cells and formed of a first interconnection extended from gate electrodes of the memory cells, second word lines corresponding to the respective first word lines, and formed of a second interconnection of a layer different from a layer of the first interconnection, and an interconnection switch provided between the first word lines and the second word lines, the interconnection switch having the first interconnection and the second interconnection cross each other, and configured to change arrangement of at least part of the first word lines.
According to still another aspect of the present invention, there is provided a semiconductor device comprising a first region formed of a transistor having a charge-accumulating layer, a first interconnection connected to the transistor having the charge-accumulating layer, a second region formed of a transistor having no charge-accumulating layer, a second interconnection connected to the transistor having no charge-accumulating layer, and an interconnection switch provided between the first region and the second region and configured to change arrangement of at least part of the first interconnection, the interconnection switch having a multilayered interconnection structure in which first interconnection and second interconnection cross each other.